RoaLogic / ahb3lite_interconnect

AHB3-Lite Interconnect

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xrun compilation error

agrobman opened this issue · comments

when it try to compile standalone RTL as :

xrun submodules/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv rtl/verilog/*.sv

I'm getting following error:

  function slave_mask_t invert_slave_mask;
                                        |
xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
  function slave_mask_t invert_slave_mask;
                                        |
xmvlog: *E,CFBADT (../rtl/verilog/ahb3lite_interconnect.sv,197|40): Declaration in constant function uses unavailable datatype.
  parameter bit [SLAVES-1:0] ERROR_ON_SLAVE_MASK[MASTERS] = invert_slave_mask(),
                                                                            |
xmvlog: *N,CFCALL (../rtl/verilog/ahb3lite_interconnect.sv,136|76): Function invert_slave_mask treated as a constant function because of this call.
	module worklib.ahb3lite_interconnect:sv

What do I miss?

I use xcellium version 20.03-s003

The code has been compiled using the Intel, Xilinx, and Lattice design flows.
We run simulations with the Aldec and Mentor tools. Unfortunately I do not have access to the Cadence tools.
It seems like the tool doesn't like/find the type definition. You can try moving the type definition before its use. Or place the type definition in a separate package.

Richard

Hello!

Fixed the issue with the patch below.

ahb3lite_interconnect.txt

That fix mixes ANSI-style and old-style (K&R) parameter declarations. That causes problems in other tools.