Rameen Anwar's repositories
Azadi-III-PnR-MPW5-
This repo hold all of the apr file for Azadi SoC submitted in MPW5
Language:TclApache-2.0000
Language:VerilogApache-2.0000
caravel_azadi_soc_iii
https://caravel-user-project.readthedocs.io
Language:VerilogApache-2.0000
Experiment1
without extra pin
Language:VerilogApache-2.0000
Experiment3
change pin Location i0_in[37]
Language:VerilogApache-2.0000
Apache-2.0000
000
Language:VerilogApache-2.0000
mslearn-tailspin-spacegame-web
Code used in Microsoft Learn modules to support Azure DevOps
Language:HTMLCC-BY-4.0000
new
newww
Language:VerilogApache-2.0000
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Apache-2.0000
riscv-core
Single Cycle RISC-V architecture
Apache-2.0000
Apache-2.0000