Priyanshu Mishra's repositories
orca-riscv
RISC-V by VectorBlox
riscv-multi-cycle
WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*
RISCV_ISA_Formal_Spec_in_BSV
A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
LC-3
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
ridecore-superscalar-ooo-cpu
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
riscv-software-notes
Some notes on RISC-V
MiteCPU
Minimal microprocessor
OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
superscalar-processor-model
A nine-stage out-of-order superscalar processor pipeline.
TablePaste
Pasting data from the web into Mathematica
DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
TAGE-Branch-Predictor
64KB branch predictor using TAGE
Hybrid-Branch-Predictor
This branch predictor uses a hybrid technique combining perceptrons and Gshare.
Perceptron-Branch-Predictor
Perceptron-based branch predictor written in C++
Video-Course-cpu-gpu-eecs
List of Computer Science courses with video lectures.
4-way-set-associative-cache-verilog
Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
RISCV_Piccolo_v1
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
opencl-kernels
OpenCL kernels for ucb-bar hardware
DrawWaveform
A set of postscript functions for drawing waveforms
tim
A small CPU core complete with compiler and ISA specification. Eventually....
chisel-torture
A tool that generates Chisel torture tests
Verilog-caches
Various caches written in Verilog-HDL
tage
Implementation of TAGE Branch Predictor - currently considered state of the art
sparc64soc
OpenSPARC-based SoC
apbi2c
APB to I2C
uvm-testbench-tutorial-simple-adder
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology