Priyanshu Mishra's repositories
priyanshu.github.io
Personal website
awesome-generative-ai
A curated list of modern Generative Artificial Intelligence projects and services
awesome-generative-ml
A curated list of Generative AI tools, works, models, and references
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel
Chisel: A Modern Hardware Design Language
constellation
A Chisel RTL generator for network-on-chip interconnects
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cutlass
CUDA Templates for Linear Algebra Subroutines
cva6-wrapper
Wrapper for ETH Ariane Core
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
FABulous
Fabric generator and CAD tools
firrtl2
UC Berkeley Copy of the FIRRTL Compiler
gemmini
Berkeley's Spatial Array Generator
hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
I2SRV64-SS-v1
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
IsaacLab
Unified framework for robot learning built on NVIDIA Isaac Sim
libgemmini
Gemmini extensions for Spike
MyArch
📱 An app to view all supported ABI of the running device
pqr5asm
PQR5ASM is a RISC-V Assembler compliant with RV32I
pulp_cluster
The multi-core cluster of a PULP system.
Pytorch-tutorials
PyTorch tutorials for beginners
riscV-rv32-simulator
Open source ISS and logic RISC-V 32 bit project
riscv-sodor
educational microarchitectures for risc-v isa
rocket-chip
Rocket Chip Generator
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
vlsi_linkedin_index
This repo provide an index of VLSI content creators and their materials
zipcpu
A small, light weight, RISC CPU soft core