PacoReinaCampo

logisim-evolution

Digital logic design tool and simulator

gpt4all

GPT4All: Run Local LLMs on Any Device. Open-source and available for commercial use.

verilator

Verilator open-source SystemVerilog simulator and lint system

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

contiki

The official git repository for Contiki, the open source OS for the Internet of Things

or1ksim

The OpenRISC 1000 architectural simulator

riscv-isa-sim

Spike, a RISC-V ISA Simulator

qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

buildroot

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open issues or file pull requests here.

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

qiskit

Qiskit is an open-source SDK for working with quantum computers at the level of extended quantum circuits, operators, and primitives.

magic

Magic VLSI Layout Tool

inkscape

Project Website: https://inkscape.org - Code Repository: https://gitlab.com/inkscape/inkscape - Draw freely. 🖌

ahir

Algorithm to hardware compilation tools (e.g. C to VHDL).

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

doxygen

Official doxygen git repository

pandas

Flexible and powerful data analysis / manipulation library for Python, providing labeled data structures similar to R data.frame objects, statistical functions, and much more

oh

Verilog library for ASIC and FPGA designers

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

myhdl

The MyHDL development repository

kicad-source-mirror

This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.

uvm-verilator

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

wavedrom

:ocean: Digital timing diagram rendering engine

srsRAN_Project

Open source O-RAN 5G CU/DU solution from Software Radio Systems (SRS) https://docs.srsran.com/projects/project

UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

openscad

OpenSCAD - The Programmers Solid 3D CAD Modeller

ghdl-yosys-plugin

VHDL synthesis (based on ghdl)

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog