OptimusMars's repositories
hdl
HDL libraries and projects
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
enxor-logic-analyzer
FPGA Logic Analyzer and GUI
verilog-axi
Verilog AXI components for FPGA implementation
modern-cpp-template
A template for modern C++ projects using CMake, Clang-Format, CI, unit testing and more, with support for downstream inclusion.
corundum
Open source FPGA-based NIC and platform for in-network compute
wb2axip
Bus bridges and other odds and ends
verilog-dsp
Verilog digital signal processing components
static_vector
C++ static vector class template. Also might be known as fixed vector or on-stack vector.
fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
tcl_for_fpga
TCL scripts for FPGA (Xilinx)
fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
Utils
Utilities for C++ for Embedded
VivadoScripting
Python Utilities to use Xilinx Vivado Tools from Python Scripts
nco
Configurable NCO (numerically controlled oscillator) written in MyHDL using a pipelined CORDIC implementation
wpseyes
Tool for bruteforce Wi-Fi WPS
FFT-cordic-HDL
FFT implementation using CORDIC algorithm written in Verilog.
pastilda
open-source password manager
fpga-hash-table
Simple hash table on Verilog (SystemVerilog)
verilog-flowgen
Ethernet flow generator framework
ddr2_sdram
DDR2 SDRAM Controller