OptimusMars's repositories
OptimumFPGAFramework
Crossplatform FPGA Framework
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
compile-time-init-build
C++ library for composing modular firmware at compile-time.
cpp_register
safe, no-cost and easy-to-use Cpp header to work safely with HW registers
embeddedsw
Xilinx Embedded Software (embeddedsw) Development
embedded_printf_traces
Compile-time optimized format and traces for bare-metal project with compile-time checks
etl
Embedded Template Library
FPGA-FixedPoint
A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
fpu
IEEE 754 floating point library in system-verilog and vhdl
fsm
Finite State Machine
GhostSD
GOST-based SDSC-card encryptor
litescope
Small footprint and configurable embedded FPGA logic analyzer
meta_types
Meta type operations that I could not find in std
parametrizable-floating-point-verilog
Verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
protothreads-cpp
Protothread.h, a C++ port of Adam Dunkels' protothreads library
python-telegram-bot
We have made you a wrapper you can't refuse
QuickPID
A fast PID controller with multiple options. Various Integral anti-windup, Proportional, Derivative and timer control modes.
red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
surf
A huge VHDL library for FPGA development
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
verilog-pcie
Verilog PCI express components
vextproj
VEXTPROJ - the version control friendly system for creation of Vivado projects
Vitis-Tutorials
Vitis In-Depth Tutorials
Vitis_Accel_Examples
Vitis_Accel_Examples
Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
vivado-git
A git-friendly Vivado wrapper