Massine's repositories
AMBA_AXI_AHB_APB
AMBA bus lecture material
awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
Cores-SweRV
SweRV EH1 core
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
dmpvl
Dave McEwan's Personal Verilog Library
gdb_systemc_trace
gdb python scripts for SystemC design introspection and tracing
How-to-Make-a-Computer-Operating-System
How to Make a Computer Operating System in C++
kianFpgaPong
Basic Pong you can extend with rotary, sound, vga generator and autopilot
learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
litex
Build your hardware, easily!
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
projf-explore
Project F brings FPGAs to life with exciting open-source designs you can build on.
PU-RISCV
Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
ResuLLMe
Enhance your résumé with Large Language Models
RISC-V-project
Description of a RISC-V architecture based on MIPS 3000
riscV-1
Open source ISS and logic RISC-V 32 bit project
riscv-gcc-prebuilt
Prebuilt rv32i/e RISC-V GCC toolchains for 64-bit x86 Linux.
riscv_verilator_model
RISCV model for Verilator/FPGA targets
SimpleCPU
An open source CPU design and verification platform for academia
style-guides
lowRISC Style Guides
test-your-sysadmin-skills
:sparkles: A collection of *nix Sysadmin Test Questions and Answers. Test your knowledge and skills in different fields with these Q/A.
the-book-of-secret-knowledge
:zap: A collection of awesome lists, manuals, blogs, hacks, one-liners, cli/web tools and more. Especially for System and Network Administrators, DevOps, Pentesters or Security Researchers.
tvip-axi
AMBA AXI VIP
verilog-axi
Verilog AXI components for FPGA implementation
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.