Marko19907 / Low-level-programming-labs

Low-level programming assignments, "Low-Level Programming" (TDT4258) course, fall 2023.

Low-Level Programming labs

This repository contains all the labs for the low-level programming course at NTNU (TDT4258).

Lab 1: Assembly programming

• Create a palindrome checker in assembly.
• Use the ARMv7 ISA and CPUlator to run the program.
• Must be case insensitive and ignore spaces.
  • A valid palindrome can only be a single word, sentence (words separated by spaces), numbers, or alphanumeric. Examples of valid palindromes: “level”, “8448”, “step on no pets”, “My gym”, “Was it a car or a cat I saw”. Examples of strings that are not a palindrome: “Palindrome”, “First level”
• The shortest palindrome is at least 2 characters long.
• The valid characters are as follows: ‘a-z’, ‘A-Z’, ‘0-9’ and ‘ ’ (space). Special characters will not be used in test inputs.
• Implement the algorithm in a high-level language (C, Rust, or Python) as you would write assembly code to get the correct control flow.
  • Written in Rust and available here.
• The program will display the output in two different ways:
  • Light up the red LEDs: If the output is not a palindrome, light up the five leftmost LEDs. If the output is a palindrome, light up the five rightmost LEDs.
  • Write to the JTAG UART: If the output is not a palindrome, write “Not a palindrome” to the JTAG UART. If the output is a palindrome, write “Palindrome detected” to the JTAG UART box.
• This lab includes an optional task: Write numbers 0 to 100 to the JTAG UART box.

Lab 2: CPU cache simulator

• Implement a CPU cache simulator in C with the following requirements:
• The simulator should be able to simulate a direct-mapped cache and a fully associative cache.
• The simulator should support both unified and split caches.
  • Unified caches have a single cache for both instructions and data (Von Neumann architecture) while split caches have separate caches for instructions and data (Harvard architecture).
• Fixed parameters:
  • 32-bit address space
  • 64-byte cache line size
  • FIFO replacement policy for the associative caches
• Variable parameters:
  • Cache size in bytes or kilobytes and only accepting powers of two between 128 bytes and 4096 bytes
  • Cache mapping, direct-mapped or fully associative
  • Cache organization, unified or split
• Expected results:
  • The simulator should output:
    • The number of accesses to the cache
    • The number of cache hits
    • The hit rate
    • Any other information you find relevant
• Trace files:
  • Memory trace mem_trace.txt files are provided in the lab repository.
    • These will be used to test the simulator.
    • The trace files contain a sequence of memory accesses, one per line.
    • Each line contains a 32-bit hexadecimal memory address and a single character indicating the type of access, either I for instruction or D for data.
• Must be able to run on Linux.

Lab 3: Tetris on a Raspberry Pi in C

Extracted to this repository since it was a big project.