StudyLong's repositories
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
tinyengine
[NeurIPS 2020] MCUNet: Tiny Deep Learning on IoT Devices; [NeurIPS 2021] MCUNetV2: Memory-Efficient Patch-based Inference for Tiny Deep Learning; MCUNetV3: On-Device Training Under 256KB Memory
archbase
教科书《计算机体系结构基础》（胡伟武等，第三版）的开源版本
core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
bl_mcu_sdk
bl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706, BL616/BL618, BL808 and other series of RISC-V based chips in the future.
bypass-paywalls-chrome
Bypass Paywalls web browser extension for Chrome and Firefox.
cvw
Configurable RISC-V Processor
English-level-up-tips
An advanced guide to learn English which might benefit you a lot 🎉 . 可能是让你受益匪浅的英语进阶指南。
force-riscv
Instruction Set Generator initially contributed by Futurewei
ibex-demo-system
A demo system for Ibex including debug support and some peripherals
litex-boards
LiteX boards files
MegCC
MegCC是一个运行时超轻量，高效，移植简单的深度学习模型编译器
NMSIS
Nuclei Microcontroller Software Interface Standard Development Repo
onedrive-vercel-index
OneDrive public directory listing, powered by Vercel and Next.js
riscv-dv
Random instruction generator for RISC-V processor verification
SpinalWorkshop
Labs to learn SpinalHDL
subconverter
Utility to convert between various subscription format
tele-aria2-mute
A Telegram bot for controlling your aria2 server.
tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro