Lei Wang's starred repositories
CTranslate2
Fast inference engine for Transformer models
flashinfer
FlashInfer: Kernel Library for LLM Serving
ucasproposal
LaTeX Proposal Template for the University of Chinese Academy of Sciences
32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
distrifuser
[CVPR 2024 Highlight] DistriFusion: Distributed Parallel Inference for High-Resolution Diffusion Models
Stable-Diffusion-ONNX-FP16
Example code and documentation on how to get Stable Diffusion running with ONNX FP16 models on DirectML. Can run accelerated on all DirectML supported cards including AMD and Intel.
CGRA-Mapper
An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
GSOC_TensorCore
TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
allo-pldi24-artifact
Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
PIM-Toolchain
EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator