Usatyuk Vasiliy's repositories
stable-diffusion-webui
Stable Diffusion web UI
text-generation-webui
A Gradio web UI for Large Language Models. Supports transformers, GPTQ, AWQ, EXL2, llama.cpp (GGUF), Llama models.
koboldcpp
A simple one-file way to run various GGML and GGUF models with KoboldAI's UI
Sparse_Filter_Bank_Review
Sparse Channel Code based Filter Bank for Faster Than Nyquist Review from Professor Li Bin Team
trapping-sets-enumeration
Importance Sampling and Linear Programming based Enumerating and Weighing of Trapping sets in LDPC codes, ISING models and related DNN Arch( Transformer, RBM, BM, SPN und etc),
pykan
Kolmogorov Arnold Networks
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Retrieval_Head
open-source code for paper: Retrieval Head Mechanistically Explains Long-Context Factuality
neureka
2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
DVB-S2-matrices
matlab tools to convert matrices defined in DVB-S2 standard to parity-check to Quasi-Cyclic matrices
EMD-Spectrum-LDPC
Enumerate LDPC Codes extrinsic message degree (EMD) Spectrum for analyzing cycles properties sublinear and part of linear trapping sets
ESP-12-ESP8266-_Server-Room-Dweet-based-Sensors-Tracker-Temp-Humidity-Tracker-
Server-Room-ESP12(ESP8266)_Dweet-based-Sensors-Tracker-Temp-Humidity-Tracker
Server-Room-Dweet-based-Sensors-Tracker-Temp-Humidity-Tracker-
STM32F405RG based Server Room Dweet Temp Humidity Tracker
llm.c
LLM training in simple, raw C/CUDA
Density-Evolution-AWGN
Density evolution for LDPC codes construction under AWGN-channel: reciprocal-channel approximation (RCA), Gaussian Evolution, Covariance Evolution
Classical-and-Quantum-Topology-ML-toric-spherical
Spherical and Hyperbolic Toric Topology-Based Codes On Graph Embedding for Ising MRF Models: Classical and Quantum Topology Machine Learning
gpqa
GPQA: A Graduate-Level Google-Proof Q&A Benchmark
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
dory
A tool to deploy Deep Neural Networks on PULP-based SoC's
parametrizable-floating-point-verilog
Verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
RandomizedGreedyMPS
Code associated with the publication "Randomized greedy magic point selection schemes for nonlinear model reduction" by R. Zimmermann/Kai Cheng
ConstellationShapingWizard
end-to-end learning of the probabilities, constellation geometry, and demapper of a communication system
fpga-snntorch
Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.
mod-interleaveavx_multithreads-FAID
Source codes for the paper "Optimized LNS-FAID of LDPC Codes: A Hybrid Precision Decoding Approach for 50G-PON".
bigdl-llm-tutorial
Accelerate LLM with low-bit (FP4 / INT4 / FP8 / INT8) optimizations using bigdl-llm
Clock-Domain-Crossing-Synchronizers
Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing solutions in digital systems.
Synology_enable_eunit
Enable an unsupported Expansion Unit
verilog-pcie
Verilog PCI express components