LVFPGABOOK / Chapter-3-Background-Technology

One could spend a lifetime studying only FPGAs. LabVIEW FPGA users need some FPGA background but not too much and not too little. Chapter 3 provides that information and resources for further reading. One of the largest public FPGA applications is Microsoft’s use of FPGAs in their data centers. Microsoft has published many YouTube videos on their development effort. Even though they did not use Xilinx or LabVIEW FPGA, the FPGA concepts are universal.

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Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications

Chapter-3-Background-Technology

References

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[24] Vanderbauwhede, W., and K. Benkrid, High-Performance Computing Using FPGAs, New York: Springer, 2013.
[25] De Schryver, C., FPGA Based Accelerators for Financial Applications, New York: Springer, 2015.
[26] Kachris, C., B. Falsafi , and D. Soudris, Hardware Accelerators in Data Centers, New York: Springer, 2019.
[27] Sundararajan, P., “High Performance Computing Using FPGAs WP375 (v1.0),” White Paper, September 10, 2010, https://www.xilinx.com/support/documentation/white_papers/wp375_HPC_Using_FPGAs.pdf.
[28] Monmasson, E., et al., “FPGAs in Industrial Control Applications,” IEEE Transactions on Industrial Informatics, Vol. 7, No. 2, 2011, pp. 224–243.
[29] MacCleery, B., “LabVIEW FPGA Deep Neural Network Solver,” New Open Source Testbed Platform for Smart Grid and Microgrid Research: Go from Paper Design to Prototype Deployment in Days, p. 67: NI, 2016, p. 71, https://forums.ni.com/t5/Power-Electronics-Development/Webcast-New-Open-Source-Testbed-Platform-for-Smart-Grid-and/gpm-p/3615423, https://forums.ni.com/ni/attachments/ni/grp-1891/966/1/New%20Open%20Source%20Testbed%20Platform%20for%20Smart%20Grid%20and%20Microgrid%20Research.pdf.
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[31] Ayub, A. B., et al., “FPGA Based Compressive Sensing Framework for Video Compression on Edge Devices,” 2020, https://labs.dese.iisc.ac.in/neuronics/wp-content/uploads/sites/16/2020/08/VDAT2020_202.pdf.
[32] Mahmood, F., et al., “2D Discrete Fourier Transform with Simultaneous Edge Artifact Removal for Real-Time Applications,” 2015 International Conference on Field Programmable Technology (FPT), Queenstown, New Zealand, 2015, pp. 236–239.
[33] Stratoudakis, T., “Hardware Accelerated Fix Order Cancel System,” Wall Street FPGA LLC, March 2011, http://www.wallstreetfpga.com/research/fix/WallStreetFPGA_FIX_CANCEL_FPGA.pdf.
[34] Ham, T. J., et al., “Genesis: A Hardware Acceleration Framework for Genomic Data Analysis,” ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020.
[35] Zou, D., Y. Dou, and F. Xia, “Optimization Schemes and Performance Evaluation of Smith–Waterman Algorithm on CPU, GPU and FPGA,” Concurrency and Computation: Practice and Experience, Vol. 24, No. 14, 2012, pp. 1625–1644.
[36] Li, I. T. S., W. Shum, and K. Truong, “160-Fold Acceleration of the Smith-Waterman Algorithm Using a Field Programmable Gate Array (FPGA),” BMC Bioinformatics, Vol. 8, No. 1, 2007, p. 185.
[37] Chiou, D., “The Microsoft Catapult Project,” 2017 IEEE International Symposium on Workload Characterization (IISWC), Seattle, WA, 2017, pp. 124–124.
[38] Alonso, G., “FPGAs in Data Centers,” Queue, Vol. 16, No. 2, 2018, pp. 52–57. [39] Ovtcharov, K., et al., “Accelerating Deep Convolutional Neural Networks Using Specialized Hardware,” Microsoft Research White Paper, Vol. 2, No. 11, 2015, pp. 1–4.
[40] Amazon, “F1 Instances: Run Custom FPGAs in the Amazon Web Services (AWS) Cloud,” 2017.
[41] Piscitello, D. M., and A. L. Chapin, Open Systems Networking: TCP/IP and OSI, Reading, MA: Addison-Wesley, 1993.
[42] Sirowy, S., and A. Forin, Where’s the Beef? Why FPGAs Are So Fast, Microsoft Research, Technical Report, September 2008, https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/tr-2008-130.pdf.
[43] Maio, D., M. Gatta, and C. Varini, “Accelerating Large Data Modeling for Quantum Computation with GPUs,” 2019, https://amslaurea.unibo.it/20903/1/Tesi.pdf.
[44] Murphy, C., and Y. Fu, “Xilinx All Programmable Devices: A Superior Platform for Compute-Intensive Systems,” Xilinx White Paper, June 13, 2017, https://www.xilinx.com/support/documentation/white_papers/wp492-compute-intensive-sys.pdf.
[45] Vuduc, R., et al., “On the Limits of GPU Acceleration,” Vol. 13, 2010, https://www.usenix.org/legacy/event/hotpar10/tech/full_papers/Vuduc.pdf.
[46] Lee, V. W., et al., “Debunking the 100X GPU vs. CPU Myth: An Evaluation of Throughput Computing on CPU and GPU,” 37th Annual International Symposium on Computer Architecture, 2010, pp. 451–460 (https://dl.acm.org/doi/10.1145/1815961.1816021).
[47] Aktemur, B., et al., “Debugging SYCL Programs on Heterogeneous Intel® Architectures,” Proceedings of the International Workshop on OpenCL, 2020, pp. 1–10.
[48] Han, F., T. Zhu, and R. Meyer, “Basic Performance Analysis of NVIDIA GPU Accelerator Cards for Deep Learning Applications,” AMAX White Paper, 2016, https://pdfs.semanticscholar.org/45f6/a5ba7c1c337b0fe-883ba426aa69ec9f6d420.pdf. (link is broken, see link https://github.com/LVFPGABOOK/Chapter-3-Background-Technology/commit/028d11a4799d0b4ce6731a2d3e1c539c780fa77c)
[49] Wang, Y. E., G.-Y. Wei, and D. Brooks, “Benchmarking TPU, GPU, and CPU Platforms for Deep Learning,” arXiv preprint arXiv:1907.10701, https://ui.adsabs.harvard.edu/abs/2019arXiv190710701W/abstract, 2019. (PDF: https://arxiv.org/pdf/1907.10701.pdf) (see also https://github.com/LVFPGABOOK/Chapter-3-Background-Technology/commit/ea5e134990e5f1892f74107c7311702310e24050)

About

One could spend a lifetime studying only FPGAs. LabVIEW FPGA users need some FPGA background but not too much and not too little. Chapter 3 provides that information and resources for further reading. One of the largest public FPGA applications is Microsoft’s use of FPGAs in their data centers. Microsoft has published many YouTube videos on their development effort. Even though they did not use Xilinx or LabVIEW FPGA, the FPGA concepts are universal.