Beast code in Giters

Kenghsien's starred repositories

opensource-toolchain-8051

Opensource toolchain for 8051 8-bit MCU

Language:CMIT2200

engineeringladders

A framework for Engineering Managers

Apache-2.0788700

egos-2000

Envision a future where every student can read all the code of a teaching operating system.

Language:CNOASSERTION217000

bare-metal-programming-guide

A bare metal programming guide (ARM microcontrollers)

Language:CMIT282400

raspi3-tutorial

Bare metal Raspberry Pi 3 tutorials

Language:CMIT900

OSH

Code for the Operating Systems course

Language:C3000

AXI_BFM

AXI4 BFM in Verilog

Language:VerilogMIT3200

axi-bfm

AXI3 Bus Functional Models (Initiator & Target)

Language:SystemVerilog2600

100DaysOfRTL

100 Days of RTL

Language:SystemVerilog31500

TinyML-Cookbook

TinyML Cookbook, published by Packt

Language:Jupyter NotebookMIT22800

fpu

synthesiseable ieee 754 floating point library in verilog

Language:VerilogMIT50100

cores

Various HDL (Verilog) IP Cores

Language:Verilog67100

oh

Verilog library for ASIC and FPGA designers

Language:VerilogMIT113500

MAXVY_MIPI_I3C_Basic_Master_Controller_IP

It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.

Language:VerilogMIT1500

block-i3cmaster-sifive

This is a repository for Improved inter-integrated circuit master.

Language:Scala100

DeepFaceLab

DeepFaceLab is the leading software for creating deepfakes.

Language:PythonGPL-3.04650400

openc906

OpenXuantie - OpenC906 Core

Language:VerilogApache-2.030600

opene902

OpenXuantie - OpenE902 Core

Language:VerilogApache-2.012800

opene906

OpenXuantie - OpenE906 Core

Language:VerilogApache-2.012600

openc910

OpenXuantie - OpenC910 Core

Language:VerilogApache-2.0111600

gem5

The official repository for the gem5 computer-system architecture simulator.

Language:C++BSD-3-Clause155200

chisel

Chisel: A Modern Hardware Design Language

Language:ScalaApache-2.0385900

gemmini

Berkeley's Spatial Array Generator

Language:ScalaNOASSERTION73700

FPGA-CAN

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Language:VerilogGPL-3.019700

R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Language:VerilogApache-2.016000

e203_hbirdv2

The Ultra-Low Power RISC-V Core

Language:VerilogApache-2.0116200

XCryptCore

Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)

Language:Verilog3400

aes-verilog

RTL implementation of Advanced Encryption Standard (AES)

Language:Verilog300

FPGA-DDR-SDRAM

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Language:VerilogGPL-3.013400

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

Language:VerilogNOASSERTION20500