It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support. Whis is used for test your MIPI I3C basic Slave functionality in simulation.
Our Verilog Source is convered into synthesized Gate Level netlist by using Yosys Tool.
Please refer IPR Terms and Condition of MIPI Organization from www.mipi.org befor use this code into your ASIC /Simulation. Download specification from https://mipi.org/specifications/i3c-sensor-specification