JagratPatkar / RSIM

A RISC-V simulator, which can simulate the Base RV32I ISA

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RSIM

A RISC-V simulator, which can simulate the Base RV32I ISA. The simulator takes a .bin file as input, created from the RASM assembler.

Supported Instructions

R Type: ADD, SUB, SIL, SLT, SLTU, XOR, SRL, SRA, OR, AND

I Type: ADDI, JALR, SLLI, SLTI, SLTIU, XORI, SRLI, SRAI, ORI, ANDI, LW, LH, LB

S Type: SB, SH, SW

B Type: BEQ, BNE, BLT, BGE, BLTU, BGEU

J Type: JAL

U Type: LUI, AUIPC

About

A RISC-V simulator, which can simulate the Base RV32I ISA

License:GNU General Public License v3.0


Languages

Language:Rust 100.0%