H-Y-B

chisel-IDEA-demo

Awesome-SGX-Open-Source

A curated list of open-source projects that help exploit Intel SGX technology

block-inclusivecache-sifive

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-template

chisel and sbt

Gem5

riscv-linux

RISC-V Linux Port

riscv-pk

elf

linux

linux-sgx

Intel SGX for Linux*

linux-sgx-driver

Intel SGX Linux* Driver

lombok-rs

Lombok port for Rust

macrokata

Learn Macros In Rust

minimal-diplomacy

Example of Chisel3 Diplomacy

openenclave

SDK for developing enclaves

opensbi

RISC-V Open Source Supervisor Binary Interface

r-lombok-macros

r-lombok is a rust macros that automatically plugs into your editor and build tools

rCore

Rust version of THU uCore OS. Linux compatible.

riscv-glibc

RISC-V port of GNU's libc

riscv-hpmcounters

A simple utility for doing RISC-V HPM perf monitoring.

riscv-tests

riscvv-test

RISC-V vector and other assembly code examples

rocket-chip

Rocket Chip Generator

SecSMT_Artifact

The artifact for SecSMT paper -- Usenix Security 2022

sifive-blocks

Common RTL blocks used in SiFive's projects

SPEC-config

SPEC compile

spectre-attack

Example of using revealed "Spectre" exploit (CVE-2017-5753 and CVE-2017-5715)

sys

vim-config