(Original readme for the template repository here)
This repo is an experiment in using Verilog source files instead of Wokwi diagrams for TinyTapeout. If you're interested in doing the same, make sure to edit the top level Makefile and replace WOKWI_PROJECT_ID with one that you generate so it doesn't clash with this repo.
Hardware used for testing this demo project is the TinyFPGA BX, install the OSS CAD Suite and issue make under src/ to generate bitstream to load on hardware.