Morpher: An Open-Source Tool for CGRA Accelerators

Morpher is a powerful, integrated compilation and simulation framework, that can assist design space exploration and application-level developments of CGRA based systems. Morpher can take an application with a compute intensive kernel as input, compile the kernel onto a user-provided CGRA architecture, and automatically validate the compiled kernels through cycle-accurate simulation using test data extracted from the application. Morpher can handle real-world application kernels without being limited to simple toy kernels through its feature-rich compiler. Morpher architecture description language lets users easily specify architectural features such as complex interconnects, multi-hop routing, and memory organizations.

More information: WOSET 2022 Presentation (Artifact demonstration from 13.25), WOSET 2022 paper

Getting Started:

You can build morpher on your Linux machine, or user docker on MAC/Linux.

Note: Morpher requires LLVM 10.0.0 and g++ version cannot be higher than g++-v7.

build with docker

for HPCA tutorial

Download the docker file into an empty folder.
Go to the folder and Build morpher image: $ docker build ./ -t morpher. This takes around 15 minutes.
Initalize: $ docker run --name morpher_tutorial -it morpher
Start the container: $ docker start morpher_tutorial
Get into the container: docker exec -it morpher_tutorial /bin/bash
Run cd /home/hpca/tutorial and build all the submodules bash build_all.sh. This takes a few minutes.
You should be able to run this command python -u run_morpher.py morpher_benchmarks/array_add/array_add.c array_add and see "Simulation test passed!!!". This takes a few minutes.

build on your machine

Pull the code clone first: git clone --recurse-submodules https://github.com/ecolab-nus/Morpher.git
pull the latest changes of submodules.: git submodule update --remote
Install LLVM, clang, polly (for DFG Generator):

Read https://llvm.org/docs/GettingStarted.html follow https://github.com/llvm/llvm-project

git clone https://github.com/llvm/llvm-project.git
cd llvm-project
git checkout llvmorg-10.0.0
mkdir build
cd build
cmake -DLLVM_ENABLE_PROJECTS='polly;clang' -G "Unix Makefiles" ../llvm
make -j4
sudo make install

Build all the submodules: bash build_all.sh
Test Environment Dependencies: Activate python3 virtual environment pip install -r python_requirements.txt sudo apt-get install gcc-multilib g++-multilib

Compiling kernels:

Specify the target arch, dfg_type, mapping method, memory bank sizes,.. in config/<>.yaml file. (default_config file targets hycube 4x4 architecture)
Run the script: $python run_morpher.py <path to c source code in benchmark folder> <target function> <configurations(default: config/default_config.yaml)>.

Examples:

Compile and verify simple kernels on hycube 4x4:

$python -u run_morpher.py morpher_benchmarks/array_add/array_add.c array_add

Please refer the following workflow for more examples.

Compile and verify kernels from Microspeech Application:

Publications

[WOSET] Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA
(to appear in Workshop on Open-Source EDA Technology co-sponsored by ICCAD 2022)

    @article{morpher-woset2022,
        title   = "{Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA}",
        author  = {Dhananjaya Wijerathne, Zhaoying Li, Manupa Karunaratne, Li-Shiuan Peh, Tulika Mitra},
        journal = {Fifth Workshop on Open-Source EDA Technology (WOSET)},
        month   = {November},
        year    = {2022},
    }

[DAC] PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra
59th ACM/IEEE Design Automation Conference, 2022 Publicity Paper
Artifact Link

[HPCA] LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators
Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Tulika Mitra
28th IEEE International Symposium on High-Performance Computer Architecture, 2022
Artifact Link Distinguished Artifact Award

[ASPLOS] REVAMP: A Systematic Framework for Heterogeneous CGRA Realization
Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2022
Artifact Link

[TCAD] HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10) 2022

[TCAD] ChordMap: Automated Mapping of Streaming Applications onto CGRA
Zhaoying Li, Dhananjaya Wijerathne, Xianzhang Chen, Anuj Pathania, Tulika Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(2) 2022

[Book Chapter] Coarse-Grained Reconfigurable Array (CGRA)
Zhaoying Li, Dhananjaya Wĳerathne, Tulika Mitra
Book chapter in “Handbook of Computer Architecture”, Springer (Invited)

[DATE] HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele
Design Automation and Test in Europe 2021

[TECS] CASCADE: High Throughput Data Streaming via Decoupled Access/Execute CGRA
Dhananjaya Wijerathne, Zhaoying Li, Manupa Karunaratne, Anuj Pathania, Tulika Mitra
ACM Transactions on Embedded Computing Systems
Special Issue on ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2019

[ICCAD] 4D-CGRA : Introducing the branch dimension to spatio-temporal application mapping of CGRAs
Manupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh
38th ACM/IEEE International Conference on Computer Aided Design, November 2019

[A-SSCC] HyCUBE: a 0.9V 26.4 MOPS/mW, 290 pJ/cycle, Power Efficient Accelerator for IoT Applications
Bo Wang, Manupa Karunarathne, Aditi Kulkarni, Tulika Mitra, Li-Shiuan Peh
IEEE Asian Solid-State Circuits Conference, November 2019

[DAC] DNestMap : Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs
Manupa Karunaratne, Cheng Tan, Aditi Kulkarni, Tulika Mitra, Li-Shiuan Peh
55th ACM/IEEE Design Automation Conference, June 2018

[DAC] HyCUBE : A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect
Manupa Karunaratne, Aditi Kulkarni, Tulika Mitra, Li-Shiuan Peh
54th ACM/IEEE Design Automation Conference, June 2017

[ACM-TRETS] Graph Minor Approach for Application Mapping on CGRAs
Liang Chen, Tulika Mitra
ACM Transactions on Reconfigurable Technology and Systems 2014

[FPT] Graph Minor Approach for Application Mapping on CGRAs Much expanded journal version
Liang Chen, Tulika Mitra
International Conference on Field Programmable Technology, December 2012
Best Paper Award

FudanEMWLab / morpher