Beast code in Giters

Egor Chushnikov's starred repositories

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Language:SystemVerilogNOASSERTION82200

Matrix-ALU

Verilog Matrix ALU

Language:Verilog200

DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Language:VerilogMIT5100

TangPrimer-20K-example

TangPrimer-20K-example project

Language:GLSL16200

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

Language:PythonMIT183600

Python4RTLVerification

Language:Jupyter NotebookMIT11600

hdlgadgets

human-in-the-loop HDL training tool

Language:PythonMIT3100

Floating-point-arithmetic

Language:Verilog100

microprocessor-units-course

Language:C1200

pyuvm

The UVM written in Python

Language:PythonNOASSERTION35000

dekatronpc

DekatronPC - vacuum tube and cold-cathode tube based computer

Language:SystemVerilog1300

distortionhdl

Language:SystemVerilogMIT400

litex

Build your hardware, easily!

Language:CNOASSERTION285400

linux-on-litex-vexriscv

Linux on LiteX-VexRiscv

Language:PythonBSD-2-Clause56100

Tang-Nano_Tetris

Tetris on Tang-Nano FPGA

Language:GLSLMIT4300

LCD1602

Verilog module for LCD1602 (HD44780)

Language:Verilog100

systemverilog-homework

SystemVerilog language-oriented exercises

Language:SystemVerilogMIT3000

MIRISCV

Открытое RISC-V процессорное ядро MIRISCV для образовательных целей

Language:AssemblyNOASSERTION800

MinecraftHDL

A Verilog synthesis flow for Minecraft redstone circuits

Language:SystemVerilog110100