In Plus/boards/omdazz/ run
01_clean.bash Clean project
05_synthesize_for_fpga.bash Synthesize project and load ro FPGA
06_configure_fpga.bash Load project to FPGA
07_upload_soft_to_fpga.bash Upload binary using UART
You need USB-to-Serial adapter for loading binary to the FPGA Board.
01_hello_text Serial port example
01_tetris ASCII based tetris game
After build you copy code_demo.mem16 to the Plus/design directory
You can run ./07_upload_soft_to_fpga.bash directly form source folder
Toolchain shoul be installed in: /opt/riscv_native
Minimal version of GCC should be 12.1.0
To use serial port switch on S1 jumper
Original serial port
https://github.com/fpga-logi/logi-pong-chu-examples/tree/master/pong-chu-logi-edu-examples-verilog
https://onlinelibrary.wiley.com/doi/epdf/10.1002/9780470374283.ch8
"Inside An Open-Source Processor" ISBN 978-3-89576-443-1 Author, Monte Dalrymple
"Modern C." Manning, 2019, 9781617295812. ffhal-02383654 Jens Gustedt.
FPGA Prototyping by Verilog Examples Author(s):Pong P. Chu First published:11 June 2008
Contains Rust code of riscv_rt crate
$ mkdir .cargo && edit .cargo/config && cat $_
[target.riscv32ic-unknown-none-elf]
rustflags = [
"-C", "link-arg=-Tlink.x"
]
[build]
target = "riscv32ic-unknown-none-elf"
You need to install cargo binutils
and
rustup targe add riscv32i-unknown-none-elf
to build run in app:
cargo objcopy --release -- -O binary app.bin
rustup toolchain install nightly rustup override set nightly
cargo build -Z build-std=core --target riscv32ic-unknown-none-elf.json --release
python bin2hex/freedom-bin2hex.py -w16 app.bin >code.mem16
rustc -Z unstable-options --target=riscv32imac-unknown-none-elf --print target-spec-json
riscv-none-elf-objcopy.exe -O binary ../target/riscv32ic-unknown-none-elf/release/app app.bin
To load in FPGA
load.bat