Divya Sai Iruku's repositories
100daysofRTL
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
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Language:SystemVerilog000
Language:Verilog000