Chun-Feng, Chen's repositories
Block_RAM_Module_FPGAs
Block RAMs (BRAMs) provide two types: two ports or dual-ports mode on FPGAs.
LVT_Writes_Method
Live Value Table (LVT-based) techniques is increasing write ports method, and using table to track the latest address data.
2015CA-Course-NCTU---MM
NCTU-2015 fall CA course final project task.
2R1W-Memory-Design
Here offer 2R1W-based building block to proposed methodology to create multi-ported memory design. And different design to support more multi-ported level growth tree.
CO-FP-2016
NCTU EE 2016 Spring CO Final Project Basis Program
coding-with-chrome
An Educational IDE showing off various Google EDU technologies.
linux
Linux kernel source tree
nvidia-docker
Build and run Docker containers leveraging NVIDIA GPUs
oh-my-zsh
A delightful community-driven framework for managing your zsh configuration. Includes 200+ optional plugins (rails, git, OSX, hub, capistrano, brew, ant, php, python, etc), over 140 themes to spice up your morning, and an auto-update tool so that makes it easy to keep up with the latest updates from the community.
OpenCL-Headers
Khronos OpenCL-Headers
openstreetmap-website
Mirror of the Rails application powering http://www.openstreetmap.org (hosted at git://git.openstreetmap.org/rails.git)
Replication_Reads_Method
Replicating BRAMs to support multiple reads without complex control logics(multiplexor).
riscv-boom-doc
Documentation for the BOOM processor
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
rocket-chip
Rocket Chip Generator
SPIRV-LLVM
LLVM framework with SPIR-V support. It's intended to contain LLVM <-> SPIR-V converter and serve as a foundation for LLVM-based front-end compilers targeting SPIR-V.
SystemVerilogReference
training labs and examples
the-swift-programming-language-in-chinese
中文版 Apple 官方 Swift 教程《The Swift Programming Language》
tmux
tmux source code