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Cal Poly CARP (Cal-Poly-RAMP)

Cal Poly CARP

Cal-Poly-RAMP

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The Cal Poly CARP SoC Design Framework

Location:United States of America

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Cal Poly CARP's repositories

ramp-core

RAMP's out of order RV32G processor, implemented with PyMTL3

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CARPOpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

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tapeout-ci-2311

caravel-user repository for November 6, 2023 tapeout

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.github

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basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

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cal-poly-ramp.github.io

Website for the RAMP framework

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carp_pcb

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cocotbext-wishbone

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qspiflash

A set of Wishbone Controlled SPI Flash Controllers

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riscv32-csr

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sky130_sram_macros

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sram22-hammer

A configurable SRAM generator

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style-guide

The SystemVerilog style guide for the RAMP framework.

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