Arna Maity's repositories
Music-recommendation-system
A Music Recommendation System with a Serverless Architecture using Spotify APIs.
expense_tracker_api
APIs for the Expense Tracker Application
havoc-v2-rest-api
REST APIs for HavocOS Website v2
HavocOS-Web
The Havoc OS Website.
arna-portfolio
My Portfolio & Blog.
Basic-React-Boilerplate
Basic react boilerplate code for a react project.
BASIC_DS_ALGO
This repo contains a collection of my implementation of some basic data structures and algorithms.
buildstat-telegram-bot
A Telegram Bot to Monitor & Trigger Travis CI Builds (WIP)
camera_test
Sample repo.
client
Triton Python, C++ and Java client libraries, and GRPC-generated client examples for go, java and scala.
expense-tracker
A simple API for an expense tracking application along with multiple interfaces to use it.
ExpenseTrackerGUI
A simple GUI for the expense tracker application
havoc-supported-devices
This repo contains a list of devices supported by Havoc OS
havoc-v2-client
Havoc OS v2 Website Frontend.
hello-world-git
1st repository to get started with GitHub & learn Git Commands
Insect-Classification-Density-Estimation
A Repo for Insect Classification & Density Estimation System done as part of final semester project.
librecores-web
LibreCores Web Site
Linux-Kernel-Modules
Introductory Kernel Modules to know more about Kernel Programming.
OpenGenus-Code-Snippets
This repo contains all the code snippets supporting my articles on OpenGenus.
smart_card_system
Code for the implementation of a Smart Card system using Raspberry Pi
Subject-Extracts
This repo consists of the Short Extracts of the topics covered during the 8 semesters.
Verilog_Modules
This repository contains a few useful Verilog modules
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Week1-Assignment
This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments
Week2-Assignment
This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments
Week3-Assignment
This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments
Week4-Assignment
This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments