Arna Maity (Arna-Maity)

Arna-Maity

Geek Repo

Company:IIIT Bhubaneswar

Location:Bhubaneswar

Home Page:https://www.linkedin.com/in/arna-maity-b22854159/

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Arna Maity's repositories

Music-recommendation-system

A Music Recommendation System with a Serverless Architecture using Spotify APIs.

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expense_tracker_api

APIs for the Expense Tracker Application

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havoc-v2-rest-api

REST APIs for HavocOS Website v2

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HavocOS-Web

The Havoc OS Website.

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arna-portfolio

My Portfolio & Blog.

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Basic-React-Boilerplate

Basic react boilerplate code for a react project.

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BASIC_DS_ALGO

This repo contains a collection of my implementation of some basic data structures and algorithms.

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buildstat-telegram-bot

A Telegram Bot to Monitor & Trigger Travis CI Builds (WIP)

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camera_test

Sample repo.

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client

Triton Python, C++ and Java client libraries, and GRPC-generated client examples for go, java and scala.

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corobo

A bot to help newcomers onboard OS projects! It's awesome!

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DSP_LAB

This repo contains MATLAB script files made as part of DSP LAB & the project done as part of this Course.

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expense-tracker

A simple API for an expense tracking application along with multiple interfaces to use it.

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ExpenseTrackerGUI

A simple GUI for the expense tracker application

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havoc-supported-devices

This repo contains a list of devices supported by Havoc OS

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havoc-v2-client

Havoc OS v2 Website Frontend.

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hello-world-git

1st repository to get started with GitHub & learn Git Commands

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Insect-Classification-Density-Estimation

A Repo for Insect Classification & Density Estimation System done as part of final semester project.

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librecores-web

LibreCores Web Site

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Linux-Kernel-Modules

Introductory Kernel Modules to know more about Kernel Programming.

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OpenGenus-Code-Snippets

This repo contains all the code snippets supporting my articles on OpenGenus.

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smart_card_system

Code for the implementation of a Smart Card system using Raspberry Pi

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Subject-Extracts

This repo consists of the Short Extracts of the topics covered during the 8 semesters.

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Verilog_Modules

This repository contains a few useful Verilog modules

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vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

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Week1-Assignment

This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments

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Week2-Assignment

This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments

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Week3-Assignment

This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments

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Week4-Assignment

This Repo contains the files created as part of the Coursera Course Introduction to Embedded System Software and Development Environments

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