AnttiLukats

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

finn

Dataflow compiler for QNN inference on FPGAs

LeFlow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

riscv-arch-test

IntroToSpartanFPGABook

A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards

fpga_puf

:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

jtag-boundary-scanner

JTAG boundary scan debug & test tool.

mistral

Cyclone V bitstream reverse-engineering project

usb_hid_host

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

awesome-fpga-boards

:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

core_sdram_axi4

SDRAM controller with AXI4 interface

LinuxCNC-RIO

RealtimeIO for LinuxCNC based on an FPGA

wishbone

Specification of the Wishbone SoC Interconnect Architecture

DisplayPort

DisplayPort IP-core

open-ec

Opensource embedded controller firmware for sipeed boards.

freeDSP-INFINITAS

sdram

Simple fixed-cycle SDRAM Controller

GoAI

GoAI 2.0 Public Repository

FPGA_DOS

Run DOS with 8086 on FPGA

basys3

Tutorial for BeeInvaders game on the Basys3 FPGA board

axis-uart

AXI Stream UART (verilog)

remote-debug-for-intel-fpga

This is a software reference code to implement the FPGA remote debug feature. User will compile the reference code into a user space application which exchanged date with Quartus tool via TCP/IP.

pysct

Python wrapper for Xilinx's XSCT/XSDB console

cpu_soft_cores

An Inventory of mostly open-source Soft Core Processors. Although many have FPGA stats, many do not.

ulm-on-ice

ULM (Ulm Lecture Machine) on ice40

efinix_titanium_control_card

Proteus Schematics and gerbers for efinix titanium control card

YM2149_PSG_system

YM2149_PSG_system for BoxLambda

one-ware.com

Risc-V

RISC-V implementation (r32i)

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU