This is a repository for the paper "Proteus: A Pipelined NTT Architecture Generator".
It include a tool to generate parametric Radix-2 Single-path Delay Feedback (SDF) and Multi-path Delay Commutator (MDC) architectures for FPGAs.
This repository provides the source code of Proteus, a tool to generate parametric Radix-2 Single-path Delay Feedback (SDF) and Multi-path Delay Commutator (MDC) architectures for FPGAs.
All content of this repo is for academic research use only. It does not come with any support, warranty, or responsibility.
The repository is structured into two main folders, namly toolchain and vivado_projects. The first folder toolchain contains all source code file to generate test vectors via python (toolchain) as well as all Verilog/SystemVerilog files required to generate a Radix-2 SDF or MDC architecture (hw). The second folder vivado_projects contains the project-files for Radix-2 SDF and MDC for all of the
We prepared a toolchain that can be used to verify the functionality of the generated hardware. To generate you own testcases for a certain architecture and option you need to execute:
/bin/python3 /home/fhirner/Desktop/proteus/toolchain/py/ntt_demo.py <NTT_TYPE> <RADIX_TYPE> <OP> <LOGN> <LOGQ> <REDUCTION_TYPE>
In case of Radix-2 MDC OP 5 with a polynomial size of 2^4 and a coefficient size of 64 bit that uses an addshift modular reduction; use:
/bin/python3 /home/fhirner/Desktop/proteus/toolchain/py/ntt_demo.py NORMAL MDC 5 4 64 ADDSHIFT
We already prepared vivado project for each option of Proteus to simplify usage. You first have to source all vivado related scipts via
source /opt/Xilinx/Vivado/2019.1/settings64.sh source /opt/Xilinx/SDK/2019.1/settings64.sh
After sourcing all related scripts you need to start with the appropriate project file. This can be done by using:
vivado -source vivado_projects/sdf/ntt_op_1_2/project_1/project_1.xpr
The command above starts vivado with Radix-2 SDF option 1 and 2, which can take up to a few second. Now you can either start a simulation, synthesis, or implementation run. If you want to use the testcases generated by the tool chain to verify the behavior you just need to click Run Simulation on the left toolbar of vivado. This will open a simulation form that runs the simulation behaivor. We already prepared a waveform to simplify the process.
Florian Hirner - florian.hirner@iaik.tugraz.at
Ahmet Can Mert - ahmet.mert@iaik.tugraz.at
Sujoy Sinha Roy - sujoy.sinharoy@iaik.tugraz.at
The Authors are affiliated with the Institute of Applied Information Processing and Communications, Graz University of Technology, Austria