zyLiu6707 / Non-Intrusive-Trace-on-LEON3-Platform

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Non-Intrusive Monitoring on LEON3 Platform

It is recommended to read this README.md, have a look on the slide and the documentation first.

Basic Information

This repository will contain several versions of LEON3 microprocessor platform. The platform is realized on Digilent Nexys-Video FPGA board using design tool Xilinx Vivado 2017.2, Vivado 2017.3 and Vivado 2018.2

You may need the necessary to gain access to the Vivado tools.

Some codes were supported in Vivado 2017.2 but not supported in the later versions of Vivado (the design tool will report a syntax error), but they just need some simple changes to adapt to the new version of Vivado. I adjusted the code to make it correct in Vivado 2018.2. In the pcore source codes I wrote comments to indicate these adaptations.

About My Work and Non-Intrusive Tracing

LEON3 microprocessor has an original internal instruction trace interface which located inside the LEON3 CPU core. The original trace interface is connected to the instruction trace buffer which is also inside the LEON3 CPU core.

The instruction trace buffer is a circular buffer, recording the time-tag, address, result, and other information of every executed instructions. However, these records are stored in this buffer and then are sent to DSU (Debug Support Unit). Thus, the instruction traces are "buffered", causing a significant time delay. As a result, they cannot be directly sent out and transmit to an ad-hoc module (pcore) for instant error detecting.

To realize on-situ tracing, and furthermore error detecting and correcting, in this modified LEON3 platform, I designed a new trace interface. Through this new trace interface, the trace information can be directly sent out. I also created several versions of custom hardware module (pcore) connected to this new trace interface to store the trace data. With this trace interface and pcore, further verification could be realized. The pcore is also interfaces with AMBA APB bus for data exchanging.

About This Repository

The structure of this repository is:

  • Manuals:

    It contains some useful user manuals provided by Cobham Gaisler and Xilinx

    I left my notes in some of these pdf files, which may be helpful for you. If you prefer to read original user manuals without any notes, you can download them from the website link in the README.txt file in this directory.

  • LEON3_Projects

    It contains several LEON3 Vivado projects. The README.txt indicates the basc information of every version of LEON3 Vivado project. Except the "LEON3" and "LEON_with_pcore", the rest of has already had the external trace interface and a dedicated pcore to store the trace information.

    In some of LEON3 project subfolder under LEON3_Projects, there are two additional folders:

    bitstream_file, which contains the bit stream generated by Vivado. If you are using the same FPGA board Digilent Nexys-Video as mine, you could directly program your board with these bitstream if you wish;

    schematic, which has the schematic pdf files of the pcore and/or other important part of LEON3 microprocessor.

  • codeblocks

    It contains a Code::Blocks project multitraces.cbp that is for testing the custom tracing pcore in the LEON3 projects listed in the README.txt in this directory.

    You can download IDE Code::Blocks here.

To keep this project a clear structure and make sure all the files have a good match with each LEON3 platform, I re-ran most of these Vivado projects to re-generate some files (e.g., bitstream files), so some files may have the latest modified dates.


This repository will be improved for several times.

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Language:VHDL 80.8%Language:C 13.9%Language:Verilog 1.3%Language:Tcl 1.2%Language:Stata 0.8%Language:Makefile 0.8%Language:Assembly 0.6%Language:Batchfile 0.2%Language:Coq 0.2%Language:XSLT 0.1%Language:C++ 0.1%Language:Shell 0.0%Language:sed 0.0%