zxhero

Xu Zhang's repositories

gem5-CXL

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

Language:C++BSD-3-Clause17 10

Logo-recognition

2018 Big data contest(http://www.datafountain.cn), python, faster-rcnn

Language:Python2 10

simulator-cache-coherence

Language:C2 2 1

Computer-network-broadcast-STP

Language:C1 10

Gomoku-AI

AI homework, python, lasagne, theano

Language:PythonMIT1 10

HCPF-pro

A MMIO peripheral for rocket chip

Language:VerilogNOASSERTION1 10

Morpheus

CXL-attached DRAM Cache for far memory

Language:C++MIT100

rocket-project-Zynq

Language:TclNOASSERTION1 10

rocketchip_on_vcu128

Language:Coq1 30

Search-algorithm

Artificial intelligence HW

Language:C++1 10

Zkernel

A simple kernel based on MIPS ISA. A File system based on FUSE

Language:C1 10

Database-Auction-market

Language:JavaScript020

GraFF

Language:VHDL010

ArcGIS-and-QGIS-web-server

Language:HTML010

COD-bhv-sim-trace

A few efforts to help students find their bugs

Language:Verilog010

CoDAXI4XbarSimpleRef

Language:Scala010

Computer-network-router

Language:C010

cv

Language:CSSMIT000

DNS

Language:C010

freeradius-build-on-centos

freeradius3.x build on centos7

010

GraFF-chisel

Language:ScalaUnlicense000

graph500

Graph500 reference implementations

Language:CNOASSERTION010

GraphLab-HCPF

Language:C010

HPL-experiment

Language:C010

Loonson-Cup

Language:VHDL010

MIPS-CPU

Multiple cycle cpu(using verilog) based on MIPS.

MIT010

static-5-pipeline-CPU

Computer Architect(B62008H) HW, verilog, MIPS

Language:Verilog010

Unified_cache

Language:Verilog010

Vitis-Tutorials

Language:C++NOASSERTION010

zxhero.github.io

Language:HTML020