Designing Memristor-based Hardware Accelerator for Neural Network Operations
EE4002R Final Year Project Thesis (AY2022/2023)
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Abstract
The goal of this research is to design a hardware accelerator to perform common neural network operations using memristor crossbar arrays.
Memristors are passive components where its resistance can be programmed on-the-fly; this means that they act like memory elements and can perform in-memory computations when a voltage is applied across it. Putting them together, they form a crossbar array which can accelerate neural network operations by performing matrix multiplications in the analog domain.
In this thesis, the circuit architecture of the hardware accelerator is derived. The circuit functionality is simulated and verified through a SPICE backend. For validation, a MNIST classification architecture is generated, and the performance of the accelerator is evaluated by characterising the circuit noise behaviour to form a noisy neural network model. Finally, a statistical analysis is done to assess the feasibility of scaling up the crossbar array for larger neural networks.