zli87's repositories
Integrated_Circuit_Design_Laboratory_IC_Lab
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
Wishbone-to-I2C-bus-controller-IP-Verification
ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.
SystemVerilog_Coursework
These are some coursework related to SystemVerilog Design & Verification in a graduate-level course, Integrated_Circuit_Design_Laboratory_IC_Lab, at NCTU.
Processor-and-Accelerator
MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement
Architecture-of-Parallel-Computers
Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid
High_Level_Synthesis_for_FPGAs
This resource comes from UCSD’s 237C Parallel Programming for FPGAs. Currently, try to finish this tutorial through vitis_hls 2020.
Microprocessor-Architecture
Cache_Simulator, Branch_Prediction and Dynamic_Instruction_Scheduling
Verilog_Practice
This repo shows my practice of some interview questions.
caravel_user_project
https://caravel-user-project.readthedocs.io
Operating-Systems-Principles
Implement process scheduling, lock with priority inheritance, demand paging in XINU OS. All projects pass all tests
markdown_readme
Markdown - you can mark up titles, lists, tables, etc., in a much cleaner, readable and accurate way if you do it with HTML.
openMPW_mytest
my testing project