zking77's repositories
accelergy
Accelergy is an energy estimation infrastructure for accelerator energy estimations
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
corundum
Open source FPGA-based NIC and platform for in-network compute
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
FastChat
An open platform for training, serving, and evaluating large language models. Release repo for Vicuna and Chatbot Arena.
fio
Flexible I/O Tester
gem5
The official repository for the gem5 computer-system architecture simulator.
gpt_academic
为ChatGPT/GLM提供实用化交互界面，特别优化论文阅读/润色/写作体验，模块化设计，支持自定义快捷按钮&函数插件，支持Python和C++等项目剖析&自译解功能，PDF/LaTex论文翻译&总结功能，支持并行问询多种LLM模型，支持chatglm2等本地模型。兼容文心一言, moss, llama2, rwkv, claude2, 通义千问, 书生, 讯飞星火等。
grok-1
Grok open release
jsmind
a mind mapping library built by javascript
mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
Microsoft-Activation-Scripts
A Windows and Office activator using HWID / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.
MQSim
MQSim is a fast and accurons, a It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)
myhdl
The MyHDL development repository
ndctl
A "device memory" enabling project encompassing tools and libraries for CXL, NVDIMMs, DAX, memory tiering and other platform memory device topics.
nvme-cli
NVMe management command line interface.
openpiton
The OpenPiton Platform
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-isa-manual
RISC-V Instruction Set Manual
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
RSSHub
🍰 Everything is RSSible
scikit-opt
Genetic Algorithm, Particle Swarm Optimization, Simulated Annealing, Ant Colony Optimization Algorithm,Immune Algorithm, Artificial Fish Swarm Algorithm, Differential Evolution and TSP(Traveling salesman)
timeloop
Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
u-boot
"Das U-Boot" Source Tree
verilator
Verilator open-source SystemVerilog simulator and lint system
verilog-axi
Verilog AXI components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
xvisor
Xvisor: eXtensible Versatile hypervISOR