zignig / patina

minimal riscv rust runtime for a FPGA core

Minimal RISCV runtime

build environment for riscv32i on (https://github.com/cbiffle/hapenny)

An attempt at a minimal rust riscv framework for fpga control plane development

This project uses pdm so running pdm lock should install all the python packages that are needed.

For the bootloader and the firmware a rust install for riscv32i-unknown-none-elf.

minimal riscv rust runtime for a FPGA core

Language:Python 77.6%Language:Rust 21.7%Language:Shell 0.4%Language:Batchfile 0.3%Language:Verilog 0.1%