EECS 151/251A FPGA Project Skeleton for Spring 2021

Checkpoint 1: 3-stage RISC-V (rv32ui) Processor Block Design Diagram

Checkpoint 2: Fully functional 3-stage RISC-V (rv32ui) Processor

Checkpoint 3: Hardware-accelerated Convolutional Neural Network (LeNet)

Checkpoint 4: Processor Optimization (100MHz)

Stats:

Best Processor Design & Implementation: mmult CPI 1.2, clock period 9ns (Neil Kulkarni & Jennifer Zhou - team04, Hari Vallabhaneni - team02)

Best Accelerator Design & Implementation: 70x speedup over software LeNet (Robin Chu & Kaitlyn Chan - team07, Matthew Tran - team11)

Best Overall Design & Implementation (z1top_axi): mmult CPI 1.234, clock period 10ns, xcel_opt 70x speedup, LUTs: 6226, FFs: 5476, BRAMs: 115, DSPs: 15 (Matthew Tran - team 11)

Resources:

RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Deep Neural Networks Design and Examples: https://inst.eecs.berkeley.edu/~eecs151/sp21/files/EECS251Leture-JennyHuang_2021.pdf

Hardware for Machine Learning: https://inst.eecs.berkeley.edu//~ee290-2

MIT Eyeriss Tutorial: http://eyeriss.mit.edu/tutorial.html

FPGA Labs SP21: https://github.com/EECS150/fpga_labs_sp21

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Little RISC-V 3-stage Pipeline CPU

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