Zhizhen Zhong's repositories
covid-mobility
[NSDI 2021] A Social Network Under Social Distancing: Risk-Driven Backbone Management During COVID-19 and Beyond
lightning-dev
Up-to-date "dev" version -- [SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
LPSplitting
[IEEE/ACM Trans. Netw. 2019] Provisioning Short-Term Traffic Fluctuations in Elastic Optical Networks
verilog-axi
Verilog AXI components for FPGA implementation
verilog-axis
Verilog AXI stream components for FPGA implementation
aff3ct
A fast simulator and a library dedicated to the channel coding.
arrow
[SIGCOMM 2021] ARROW: Restoration-Aware Traffic Engineering
clusterdata
cluster data collected from production clusters in Alibaba for cluster management research
Deep-Compression-PyTorch
PyTorch implementation of 'Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding' by Song Han, Huizi Mao, William J. Dally
DPU-PYNQ
DPU on PYNQ
exo
Exocompilation for productive programming of hardware accelerators
FlexFlow
A distributed deep learning framework that supports flexible parallelization strategies.
ilop
Algorithms for solving Inverse Linear Optimization Problem (ILOP)
Morpheus
Morpheus SDK
oopt-gnpy
Optical Route Planning Library, Based on a Gaussian Noise Model
p4c
P4_16 reference compiler
RFSoC-PYNQ
Python productivity for RFSoC platforms
RFSoC2x2-PYNQ
RFSoC2x2 board repo for PYNQ
Shire
Framework for FPGA-accelerated Middlebox Development
tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
verilator
Verilator open-source SystemVerilog simulator and lint system
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
xfcp
Extensible FPGA control platform
xup_vitis_network_example
VNx: Vitis Network Examples
ZCU216-PYNQ
Board repo for the ZCU216 RFSOC