Guanwen (Henry) ZHONG's repositories
aiostratum_proxy
aiostratum_proxy is a modular/extensible stratum protocol mining proxy built using Python3's asyncio.
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
BOE-Hardware
BOE Hardware Design
ccp
A platform for implementing congestion control algorithms in user-space.
cpp-serializers
Benchmark comparing various data serialization libraries (thrift, protobuf etc.) for C++
ethernet_10ge_mac_SV_UVM_tb
SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
FundamentalAnalysis
Fully-fledged Fundamental Analysis package capable of collecting 20 years of Company Profiles, Financial Statements, Ratios and Stock Data of 20.000+ companies.
jvm-serializers
Benchmark comparing serialization libraries on the JVM
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
mobile-deep-learning
This research aims at simply deploying CNN(Convolutional Neural Network) on mobile devices, with low complexity and high speed.
ofp
OpenFastPath project
PYNQ-Networking
Networking Overlay on PYNQ
stellar-core
stellar-core is the backbone of the Stellar network. It maintains a local copy of the ledger, communicating and staying in sync with other instances of stellar-core on the network. Optionally, stellar-core can store historical records of the ledger and participate in consensus.
streaming-benchmarks
Benchmarks for Low Latency (Streaming) solutions including Apache Storm, Apache Spark, Apache Flink, ...
XRT
Xilinx Run Time for FPGA