zhenghaolu

zhenghaolu

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IHP-Open-PDK

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

Language:HTMLLicense:Apache-2.0Stargazers:354Issues:25Issues:70

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Language:PythonLicense:Apache-2.0Stargazers:272Issues:20Issues:209

OpenSERDES

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Language:VerilogLicense:GPL-3.0Stargazers:133Issues:12Issues:7

Inverter-design-and-analysis-using-sky130pdk

Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools

Language:ShellStargazers:86Issues:4Issues:0

open-source-pdks

Index of the fully open source process design kits (PDKs) maintained by Google.

volare

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs

Language:PythonLicense:Apache-2.0Stargazers:59Issues:9Issues:28

openPCells

Parametric layout generator for digital, analog and mixed-signal integrated circuits

Language:CLicense:GPL-3.0Stargazers:48Issues:7Issues:13

TIGFET-10nm-PDK

An open source PDK using TIGFET 10nm devices.

Language:ShellLicense:MITStargazers:43Issues:10Issues:0

svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language:SystemVerilogLicense:MITStargazers:42Issues:7Issues:7

msdsl

Automatic generation of real number models from analog circuits

Language:PythonLicense:MITStargazers:36Issues:10Issues:19

Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

Language:VerilogStargazers:36Issues:1Issues:0

anasymod

A framework for FPGA emulation of mixed-signal systems

Language:PythonLicense:BSD-3-ClauseStargazers:33Issues:8Issues:35

zeropdk

Zero PDK: python-based support for open source PDKs

Language:PythonLicense:MITStargazers:26Issues:8Issues:2

eFPGA---RTL-to-GDS-with-SKY130

This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk

Language:VerilogLicense:Apache-2.0Stargazers:24Issues:5Issues:0

sar-adc

Model SAR ADC with python!

Language:Jupyter NotebookStargazers:17Issues:3Issues:2

Adafruit_CircuitPython_MCP4725

CircuitPython module for the MCP4725 12-bit digital to analog converter.

Language:PythonLicense:MITStargazers:11Issues:21Issues:7

Behavior-modeling-of-PLL

MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/

Language:MATLABLicense:MITStargazers:7Issues:2Issues:0

ECIF

An Equivalent Circuit model Impedance Fitting program

Language:PythonLicense:BSD-3-ClauseStargazers:6Issues:1Issues:11

reflow

Analog/Digital/Mixed Signal Simulation Flow

Mixed-signal-Two-Step-Flash-ADC

This circuit is a part of Mixed Signal SOC design.

Language:VerilogLicense:GPL-3.0Stargazers:5Issues:1Issues:0

circuitrylib

CircuitryLib is a Python library for creating, modelling various сircuit engineering system including output to LaTeX and graphical representations (digital logic circuits for now).

Language:PythonLicense:MITStargazers:5Issues:8Issues:0

Graduation-Thesis

Placement Algorithm Design and Implementation for Analog and Mixed-signal Integrated Circuits

Language:C++License:MITStargazers:4Issues:2Issues:0

Adafruit_CircuitPython_ADT7410

A circuitpython library for the Analog Devices ADT7410 temperature sensor

Language:PythonLicense:MITStargazers:3Issues:20Issues:4

lib_sw_pll

Software Phase Locked Loop

Language:PythonLicense:NOASSERTIONStargazers:2Issues:6Issues:15

analogcircuits

AnalogCircuits is for using Python as a quick analog circuits design tool.

Language:PythonLicense:MITStargazers:1Issues:1Issues:0

pll-simulator

Phase Lock Loop Simulator

Language:PythonStargazers:1Issues:2Issues:0

AI-in-Analog-Circuit-Design

In this project, the Ocean and Python Scripts are used to optimized the circuit in Analog IC Design

Language:PythonStargazers:1Issues:1Issues:0

D-Razavi_Analog_CMOS_python

This is a project intends to model and visualize the Analog circuit structure described in Behzad Razavi 's Design of Analog CMOS Integrated Circuit (second edition) using Python.

Language:Jupyter NotebookStargazers:1Issues:1Issues:0

amcd

HSB MScEE M 2.9 Analogue Mixed-Signal Circuit Design

Language:MATLABLicense:MITStargazers:1Issues:1Issues:0

msvsdpim

Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.

Language:PythonStargazers:1Issues:1Issues:0