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TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.

Language:C++MIT14800

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

Language:PythonMIT11300

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Language:C++MIT11700