zhanghaim's starred repositories
AXI4_Interconnect
AXI总线连接器
I2C_UVM_APB
Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface
SPI
Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.
UVM-APB_RAL
This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
SystemVerilog-Bitmap-Library-AXI-Image-VIP
Bitmap Processing Library & AXI-Stream Video Image VIP
Verification-of-AHB-Lite-Memory
Project for course EE-599B: SoC Verification in System- Verilog
riscv-rv32im-core
System Verilog Implementation of a basic Risc-V core.
system-verilog-scoreboard
Simple system verilog program with a testbench example
UVM_based_Verification_of_APB_protocol
APB Protocol is designed and verified using System Verilog based UVM. The tool used in designing and simulation is EDA Playground.
RISC-V-Single-Cycle-Datapath-in-System-verilog
rv32i implementing all base instructions.
System-Verilog-Packet-Library
System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
SystemVerilogAssertions
Examples and reference for System Verilog Assertions
SystemVerilogReference
training labs and examples
caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
system_verilog-labs
Digital IC Verification, using system Verilog to verify the functions of preprocessing module and ALU
ExtremeDV_UVM
UVM resource from github, run simulation use YASAsim flow
Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
digital_ic_verification
数字IC验证案例（SV and UVM）
SystemVerilog
SystemVerilog examples and projects
UVM-Examples
UVM examples and projects