zhanggd

apb

APB Logic

apb_gpio

apb_node

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi2apb

axi_mem_if

Simple single-port AXI memory interface

axi_node

AXI X-Bar

axi_slice

Pipelines the AXI path with FIFOs

axi_slice_dc

AXI Dual-Clock FIFO for clock domain crossings (CDC)

chisel3

Chisel 3

fpga-support

IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs

fpu

IPApproX

Set of IP management tools used within the context of the PULP project

pulp-riscv-binutils-gdb

pulp-riscv-gcc

pulp-tools

pulpino

An open-source microcontroller system based on RISC-V

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

riscv

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv-fesvr

RISC-V Frontend Server

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-opcodes

RISC-V Opcodes

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-tests

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

riscv-torture

RISC-V Torture Test

rocket-chip

Rocket Chip Generator

zero-riscy