Zero ASIC's repositories
switchboard
Communication framework for RTL simulation and emulation.
wildebeest
RTL logic synthesis
ebrick-demo
Demo: how to create a custom EBRICK
logikbench
Parametrized suite of Verilog RTL benchmarks.
Communication framework for RTL simulation and emulation.
RTL logic synthesis
Demo: how to create a custom EBRICK
Parametrized suite of Verilog RTL benchmarks.