zeeshandildar

Design-Pattern-in-SV

This repo is created to includes illustrative examples on oop design pattern in SV

fwrisc

Featherweight RISC-V implementation

General

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Practical-UVM-Step-By-Step

This is the main repository for all the examples for the book Practical UVM

Simple_alu_uvm_testbench

Simple_UVM

Implements a simple UVM based testbench for a simple memory DUT.

uvm-testbench-tutorial-simple-adder

A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

vimrc

The ultimate Vim configuration (vimrc)

zeeshandildar

Config files for my GitHub profile.