zaoqi-unsafe / cpus-caddr

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

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cpus-caddr

Verilog FPGA re-implementation of MIT CADR lisp machine

This is a re-write of the MIT CADR verilog, with more rational clocking and synchronous rams.

It includes a little nios cpu which was used to debug the dram and mmc code.

It boots a load band and runs as a lisp machine.

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FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Languages

Language:Verilog 66.6%Language:VHDL 7.7%Language:C 4.9%Language:Tcl 4.7%Language:Shell 4.6%Language:SystemVerilog 3.0%Language:Common Lisp 2.1%Language:Stata 1.9%Language:HTML 1.7%Language:Coq 1.0%Language:Batchfile 0.7%Language:C++ 0.7%Language:M 0.2%Language:MATLAB 0.1%Language:Makefile 0.1%Language:Roff 0.0%Language:Assembly 0.0%