Giters
zachjs
/
sv2v
SystemVerilog to Verilog conversion
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Stargazers:
536
Watchers:
16
Issues:
270
Forks:
52
zachjs/sv2v Issues
Missing "wire" keyword
Closed
2 months ago
Comments count
2
Assert Property ```disable iff``` not fully converted to Verilog
Updated
2 months ago
Comments count
1
SV2V QA test suite
Updated
2 months ago
Comments count
5
[Feature Request] Copy comments over
Updated
3 months ago
Comments count
3
Non-exhaustive patterns in Part _ _ Module _ name _ _ with --write=DIR option
Closed
3 months ago
Comments count
5
Add support for `disable` statement
Updated
3 months ago
Comments count
4
Integration with SVase?!
Updated
3 months ago
Comments count
6
How to build on GNU/Linux on ppc64?
Closed
3 months ago
Comments count
9
How to build on GNU/Linux on arm64?
Closed
3 months ago
Comments count
16
File name too long
Closed
4 months ago
Comments count
3
Build fails on MacOS
Closed
5 months ago
Comments count
2
regarding system verilog to verilog
Updated
5 months ago
Comments count
8
LLVM dependency
Closed
5 months ago
Comments count
4
Automatic Function Produces Construct with Infinite Loop in Yosys
Updated
6 months ago
Comments count
4
Support for `unique` and `priority`
Closed
6 months ago
data type `string` not removed from module item
Closed
7 months ago
Comments count
4
Option to Convert Procedural Blocks to Modules
Closed
8 months ago
Converted Verilog Outputs Different Result Compared to Original SysVerilog
Closed
8 months ago
Comments count
3
SV2V automatically removes parentheses in operator precedence
Closed
8 months ago
Comments count
6
fork-join with wait produce a parse error
Closed
8 months ago
Comments count
2
Convert severity tasks to Verilog
Updated
8 months ago
Comments count
3
Mutidimensional Packed Arrays Handler Does Not Match Commercial Synthesis Tools
Updated
8 months ago
Comments count
1
Token '#' issue in wire definition and assignment
Closed
8 months ago
Comments count
1
Streaming operator is not converted when combined with conditional operator
Closed
8 months ago
Comments count
2
Different types in generate branches results in error
Updated
9 months ago
Comments count
2
Width extension converts string to int and changes endianess / byte order
Closed
9 months ago
Comments count
2
`input reg` is not allowed in Verilog
Closed
10 months ago
Comments count
2
Would you please implement those enum methods for SystemVerilog ?
Updated
10 months ago
Comments count
1
[feature request] support for field name preservation when struct conversion
Updated
10 months ago
Comments count
6
package import declaration not work?
Closed
10 months ago
Comments count
3
name conflict
Closed
10 months ago
Comments count
4
Issue with $clog2 of a parameter
Closed
a year ago
Comments count
3
Unexpected interface mismatch error when using "modport"
Closed
a year ago
Comments count
2
Array literals flow into Verilog unchanged
Updated
a year ago
'parameter type' refers to wrong type
Closed
a year ago
Comments count
3
using interface arrays generates broken code
Closed
a year ago
Comments count
13
False incompatible bus size error on output and reg
Closed
a year ago
Comments count
9
Issues with newest iverilog
Closed
a year ago
Comments count
3
Attributes in expressions
Closed
a year ago
Comments count
2
ifndef and define behavior not compatible with Verilog
Closed
a year ago
Comments count
5
sv2v: unexpected non-var or non-port function decl
Closed
a year ago
Comments count
2
`parameter type`s for `interface`s not working with types that have been defined using `typedef`
Closed
a year ago
Comments count
4
Feature request: Documentation for contributing and writing tests
Closed
a year ago
Comments count
1
Struct parameters in module definition
Closed
a year ago
Comments count
6
Issue with hierarchical cast not accepted by Yosys
Closed
a year ago
Comments count
4
newest iverilog crashes when running tests
Closed
a year ago
Comments count
4
error: warning: passing 'char *' to parameter of type 'const unsigned char *' converts between pointers to integer types where one is of the unique plain 'char' type and the other is not [-Wpointer-sign]
Closed
a year ago
Comments count
4
Make test prints a lot of warnings
Closed
a year ago
Comments count
2
Problems building
Closed
a year ago
Comments count
3
Missing empty port connection in output file
Closed
a year ago
Comments count
2
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