yzwangfeng / DOM

Dual-output LUT/gate merging during technology mapping

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DOM

This is a project for dual-output gate merging.

FPGA: dual-output LUT merging

ASIC: dual-output gate merging

FPGA

ASIC

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Dual-output LUT/gate merging during technology mapping


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Language:C++ 73.7%Language:Verilog 25.6%Language:Makefile 0.8%