yw19e14's repositories
WANG
DPU-Xilinx-log
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
Visual-Tracking-Development
Visual Object Tracking
resnet_py
Datasets, Transforms and Models specific to Computer Vision
KCFcpp
C++ Implementation of KCF Tracker
modbus_crc_verilog
FPGA纯逻辑实现modbus通信
CPlusPlusThings
C++那些事
ZYNQ
⚙️ 基于 Zynq-7 全可编程 SoC 的设计
yolov3
YOLOv3 in PyTorch > ONNX > CoreML > TFLite
keras-yolo3
A Keras implementation of YOLOv3 (Tensorflow backend)
Python-100-Days
Python - 100天从新手到大师
sha512
Verilog implementation of the SHA-512 hash function.
dpu_on_zcu102
The Guidance For Installing dpu and some other stuff On Xilinx ZCU102
cordic
An implementation of the CORDIC algorithm in Verilog.
HashCalculator
Helper tool to calculate hashes of data
FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
aes128-hdl
A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
md5_core
MD5 core in verilog
verilog-sha256
Implementation of the SHA256 Algorithm in Verilog