The simple 32-bit RISC-V core written in SystemVerilog.
Running on Basys3 FPGA Evaluation Board
- 5 clocks per instruction (1 clock for each of the 5 stages: fetch, decode, execute, memory access, and write back)
- Pipeline omitted
- Instruction set: RV32I
- Omit privileged instructions and interrupt area
- Generated hexadecimal instruction sequence is embedded in instruction memory using $readmemh of SystemVerilog
- Specify file name ($readmemh) /home/isaka/...
- Display the value of a0 register in decimal on 7-segment LED
- test/test.c... Execute a program to find the tenth term of the Fibonacci sequence by recursion
- test/start.S... Specify to call main without doing anything (if compiled normally, an initialization routine with unimplemented instructions will be run)
- test/link.ld... Specify that the instruction is executed from address 0.
- test/Makefile... .hex file,dump file generation automation
- test/test.hex... ...instruction sequence to be executed by CPU in hexadecimal, 4 bytes in a row.
- test/test.dump.... Result of reverse assembly of test.elf (confirming that the program is an infinite loop of `8c' after finding Fibonacci numbers by recursion)
$ make <name of C file you want to test>.
Example
$ make fib
→ fib.c is compiled for RISC-V.
// The following, if necessary.
// sudo chmod 777 test.hex