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DirectNVM

An open-source RTL NVMe controller IP for Xilinx FPGA.

dram_sim_model

A Xilinx DDR3 simulation model wrapper logic.

LRUCache

Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.

rtl_template

A template folder for Vivado RTL project, including .gitignore.

SudokuSolver

alpine-vim

"dockerized" Vim

blog-image-repo

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

CatSlaveSaver

Ball pick-up robot to save your life when playing with your cat.

cppsiphash

SipHash C++11 header-only library

CTREncryption

Cache-enabled counter encryption, written in Vivado HLS.

dockerized-vim

drawio

draw.io is a JavaScript, client-side editor for general diagramming and whiteboarding

fpga-drive-aximm-pcie

Example designs for FPGA Drive FMC

getgist

🖥️ Easily download any file from a GitHub Gist, with one single command.

hexo-theme-Wikitten

A theme of Hexo for Wiki seem like Wikitten style.

hls_template

A template folder for Vivado HLS project including .gitignore.

nanoGPT

The simplest, fastest repository for training/finetuning medium-sized GPTs.

non-stencil-loop-benchmarks

Benchmarks used in our FPGA'19 paper

pyxsi

Python/C/RTL cosimulation with Xilinx's xsim simulator

rosetta

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

siphash-verilog

Verilog implementation of pipelined 64-bit SipHash2-4 hash function

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

vim_conf

vitis-mre

Minimal reproducible example.

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

yu-zou

zhenye-na

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