yrabbit / road-to-linux

Road to Linux on RISC-V in Verilog

an accessible way of learning system bring-up

RLSoC dual core

Status

• only one core is active at a given moment of time
• easily switch between single and dual core by using a flag
• ported to the cheap Tang nano 20k board
  and a couple of bugs solved in 20231103 version
  (you must install GoWin EDA education build
  and add gowin/IDE/bin folder to your system path)
• rlsoc-tn-20231103.tgz
• in order to understand dual-core you should first understand the ebook below
• 25 pages dedicated chapter in the book
• https://youtu.be/Ce9SjgnXosQ
• the buyers of previous versions have free access to the last version; just send me an email with your version of the book at laurentiu dot duca at gmail dot com and please write the date when you have bought it

Simulation in verilator

• first, compile bbl

cd rlsoc-tn/riscv-pk-build
../riscv-pk/configure --enable-logo --enable-print-device-tree --host=riscv32-buildroot-linux-gnu --with-arch=rv32imac --with-payload=../linux-kernel/vmlinux
make

• patch linux arch/riscv/kernel/sbi.c and add the ipi clear function

static const struct riscv_ipi_ops sbi_ipi_ops = {
        .ipi_inject = sbi_send_cpumask_ipi,
        .ipi_clear  = sbi_clear_ipi
};

• compile linux and rootfs (by using the configure files from linux-kernel folder) and copy vmlinux to rlsoc-tn/linux-kernel
• run the simulation in verilator

cd rlsoc-tn/rvsoc_src_ver053/src
./run-sim.sh

Initial RLSoC

Notes

• initial RLSoC sources are rvsoc_src_ver053-20220521-1310.tgz
• for Verilator 5, in src/Makefile must be appended -Wno-LATCH to VERIFLAGS:

VERIFLAGS += -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-COMBDLY -Wno-LATCH

• in src/run-sim.sh replace

cd /home/laur/lucru/cn/riscv/rvsoc-site-japan/initmem_gen2
with
cd ../../initmem_gen2
and
cd /home/laur/lucru/cn/riscv/rvsoc-site-japan/rvsoc_src_ver053/src
with
cd ../rvsoc_src_ver053/src

• for SIM_MODE, the time to boot is greater than 80000000 clock cycles
• demo video on youtube
  https://www.youtube.com/watch?v=1YQXtjbE5Q8

Book description for RLSoC

• ebook, 216 pages at 12 euro price
• RLSoC single and dual core
• https://books.google.ro/books/about?id=lEVxEAAAQBAJ&redir_esc=y&hl=en
• The book presents the architecture of the RLSoC single and dual core project and the TinyEMU simulator. It covers building, interactive simulation and implementation aspects. In the book are described the RISC-V32 processor, MMU, memory controller, console and interrupts. We dig into the Linux kernel and see how it manages boot-up and hardware interaction.
• the book is written based on my notes taken when I tried to understand rvsoc and tinyemu and is based on commented code excerpts
• it is a book to be read thorough
• this version is forked from RVSoC v53, is written in Verilog and implements RISC-V32 with MMU, console and uses Linux initramfs disk.
• it is ported on Tang Nano 20k, Nexys A7, Arty A7 FPGA boards

Reader's profile

• level: intermediate to advanced
• should be skilled in assembler, C, verilog and computer architecture
• should have the ability to read pseudocode

Contents

Please also see the table of contents:
https://github.com/laurentiuduca/road-to-linux/blob/master/table-of-contents.pdf

About the author

Laurentiu-Cristian Duca is an open source software enthusiast passioned on the Linux operating system and FPGA programming. He started and is currently envolved in open source projects like rtnet-preempt_rt, iot-ota-sus, openVeriFLA and other. Laurentiu is skilled in C, verilog, assembler, Linux and computer architecture. He has a diploma in computer science and engineering and has got a PhD in software for electrical devices.