younghogong's repositories
spikingjelly
SpikingJelly is an open-source deep learning framework for Spiking Neural Network (SNN) based on PyTorch.
ece695-2021
Programming and Assignment Material for ECE 695
tiny-dnn
header only, dependency-free deep learning framework in C++14
models-comparison.pytorch
Code for the paper Benchmark Analysis of Representative Deep Neural Network Architectures
OpenGraphSim
OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.
MAVBench
Simulator + benchmark suite for Micro Aerial Vehicle design.
marss-riscv
Micro-ARchitectural Full System Simulator for RISC-V
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
rocketchip_refactored
This contains a refactored Rocket Chip, which supports the latest versions of Chisel3, FIRRTL and Plugins
riscv_vhdl
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
SimpleSSD-FullSystem
Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations
SimpleSSD
Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations
Python
My Python Examples
Ripes
A graphical 5-stage RISC-V pipeline simulator & assembly editor
digital-flow
This is a tutorial on standard digital design flow
test-cuda-vs-code
This is to test cuda c/c++ code in vs-code in windows.
CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
vivado_hls
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Hi-DMM
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
CACTI3DD-for-viamodeling
Via modeling
verilog-ethernet
Verilog Ethernet components
Personalized-Page-Rank
Serial and parallel PPR.